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Mühendislik Mimarlık Fakültesi - Bolumderslericerik Muhendislik
Course unit title Level of course unit Course unit code Type of course unit L+R C ECTS
Digital Design with Verilog Hdl BIM-304 Compulsory 6 3 6

Description of course unit

Prerequisites and course requisities
Language of instruction Turkish
Coordinator
Lecturer(s)
Teaching assitant(s)
Mode of delivery Face to face
Course objective This course aims to teach the student enrolling this class: the importance of hardware description languages, combinational and sequential circuit design and simulation with Verilog, writing testbenches, RTL design, datapath design and controller design, synthesis, rules for writing synthesizable Verilog codes.
Course description

Course contents

1- Installing XILINX ISE program into the computer, coding and compiling the full adder circuitry as the first Verilog program, creating a testbench, simulating the adder using XILINX ISIM simulator.
2- Hardware description languages, levels of digital circuits design, design methodology and flow, synthesis, high level synthesis, logical synthesis, physical synthesis, libraries, constraints, specification, simulation.
3- Verilog identifiers, comments, numbers, logical values, bitwise operators, logical operators, relational operators, arithmetic operators, concatenation operators, bit vectors, wire and reg variables.
4- Continuous assignments, procedural assignments, primitives, modules, ports, module instances, structural modules, behavioral modules, initial and always blocks, control structures, if statement, case statement.
5- Structural multiplexer, behavioral multiplexer, structural full adder, repetition, for and while statements.
6- Blocking and non-blocking procedural assignments.
7- Combinational circuit design, sensitivity list.
8- Combinational circuit design, sensitivity list.
9- D Flip-flop with synchronous reset and preset, D flip flop with asynchronous reset and preset.
10- RTL design, datapath design, controller design.
11- RTL design, datapath design, controller design.
12- Synthesizable and non-synthesizable Verilog codes, design rules for synthesizable Verilog programs.
13- Designing a processor with Verilog.
14- Designing a processor with Verilog.
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Learning outcomes of the course unit

1- The student will learn the importance of hardware description languages.
2- The student will learn the structure of Verilog.
3- The student will design and simulate combinational and sequential circuits with Verilog.
4- The student will write testbenches.
5- The student will learn another hardware description language like VHDL easily.
6- The student will learn different levels of digital circuit design.
7- The student will design RTL (datapath and control unit).
8- The student will learn the fundemantals, levels and components of synthesis.
9- The student will write synthesizable Verilog codes.
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